With the advent of advanced technology nodes, it is no longer possible to use conventional photolithography techniques to accurately pattern the geometries required for 20 nm process nodes and below. Therefore, foundries have turned to various multi-patterning lithography techniques to address this issue. With these multi-patterning techniques, shapes on the same layer manufactured with multi-patterned technology (MPT) are created through multiple exposures using multiple masks.
Physical design tools must be able to assign shapes on an MPT process layer to a specific mask so that they can check mask-based physical design rule rules to ensure that the design can be fabricated. Physical design tools therefore often include extensions that are able to represent MPT information. The extensions support assigning mask “colors” to shapes and vias, where different colors indicate the usage of a different photolithographic mask.
Numerous techniques may be employed to implement a multi-patterning approach that implements multiple colors for lines and metal cuts. SADP (self-aligned double patterning) and SAQP (self-aligned quadruple patterning) are both examples of multi-patterning approaches that can be used to manufacture modern electronic circuit designs. SADP and SAQP are described here merely as illustrative example of multi-patterning techniques, and it is expressly noted that the inventive concepts described herein are applicable to multiple types of multi-patterning technologies and are not restricted only to SADP and SAQP technologies.
Using multiple core masks often give rise to systematic or non-systematic alignment or overlay issues between the multiple core masks. Recent developments avoid such alignment or overlay issues by using a core mask and a trim mask (or block mask) for each layer to be printed on a lithographic system.
For multi-patterning processing (e.g., using either SADP or SAQP), the core mask is used to create a core layout (also referred to as a “mandrel” layout) to implement mandrels, which are the printed patterns generated by the core mask. Deposition of sidewall materials is then performed, followed by removal of certain portions of the core and/or sidewall materials (depending upon the specific design and the type of processing that is performed). Trimming is then performed using the trim mask. Application of the trim mask forms a “gap” between shapes on the circuit layout, where the term “gap” may also be referred to as “TrimMetal”, “CutMetal”, “trim shape”, and/or “trim layer shape”, depending upon the terminology used by the specific fabrication facility that manufactures the electronic design (with these terms being used herein inter-changeably).
An integrated circuit designer may use a set of EDA application programs to create a physical integrated circuit design layout with regards to the multi-patterning process. The EDA application implements layout designs having geometric shapes of different materials to create the various electrical components on an integrated circuit and to represent electronic and circuit IC components as geometric objects with varying shapes and sizes.
After an integrated circuit designer has created an initial integrated circuit layout, the integrated circuit designer then verifies and optimizes the integrated circuit layout using a set of EDA testing and analysis tools. Verification may include, for example, design rule checking (DRC) to verify compliance with rules established for various IC parameters. It is noted that such rule checking may also be performed during the design process (e.g., during the placement/routing process) to create correct-by-construction designs.
With the advent of 32 nanometer (nm) technology and beyond (e.g., 22 nm, 14 nm, 10 nm, 7 nm, etc.), the trim mask often requires its own design rules. With these rules, the properties of the gaps between objects formed by the trim mask are checked to ensure compliance with design requirements promulgated by the foundry or fabrication facility that will be responsible for using the mask to manufacture the electronic product. For example, these rules will be used to make sure appropriate spacing exists between metal ends in the layout with regards to the trim mask gaps.
With deep submicron designs, a fabrication facility may now require the gap shapes in the design to be materialized as a gap shape object for each of the gaps that will be formed in the design by the trim mask. The reason for this is because the fabrication facility may need the existence of these gap shape objects to implement finer grained design rule checking of the gaps formed by the trim masks.
However, requiring these gap shapes to be materialized as actual objects having the relevant shape properties of the gap creates a significant amount of computational and storage expense for the EDA processing application. This is because a modern electronic design may have a very large number of layout objects, which corresponds to an extremely large number of gap shape objects for which storage space needs to be allocated and maintained. In addition, each edit to the layout that modifies a pertinent layout object, e.g., editing the location or dimension of a wire object, will now require the additional expense of editing each and every gap shape object that is affected by the edit to the corresponding wire, e.g., to edit the location, width, and/or height properties of the gap shape when its adjacent wire shape is edited. For a modern electronic design having a large number of layout objects (e.g., having hundreds of millions or even billions of transistors and corresponding wiring), the level of overhead to implement and maintain gap shape objects could negatively affect the operation and performance of the EDA software tools, potentially adding excessive amounts of time delays to the process of generating and verifying the circuit design.
Therefore, there is a need for an improved approach to implement trim data representations for an electronic design that avoids these and other problems.